Many devices in widespread use today incorporate low-power circuits. In contrast, certain portions of the circuitry within these low-power devices have a requirement for high-voltage functionality. For example, non-volatile memories require voltage levels for reading and programming operations that far exceed a voltage level available from the power supply. Additional circuitry, such as a charge pump, is able to boost electrical charge to a voltage level exceeding that provided by the power supply. In order to perform the voltage boosting function, the charge pump must be supplied with a correct voltage level to operate properly.
Most circuits require a minimum voltage supply level before proper operation may be realized. Without at least a proper minimum power supply voltage level being available, circuitry may perform incorrectly or produce unexpected results. Power-on control circuits have typically used a voltage supply level detector and have compared that level with an internal reference. The internal reference typically has a dependence on internal device thresholds, an ability of accurately tracking electrical characteristics in the device, and on temperature and processing variation.
FIG. 1 is a prior art system block diagram of a device incorporating threshold detection power-on sequencing 100. An output of a VCC detector 110 is connected through a VCC status line 115 to the respective inputs of a bandgap voltage reference 140, a read charge pump, 150, and a circuit block 160. Each one of the bandgap voltage reference 140, the read charge pump, 150, and the circuit block 160, for example, are connected to a VCC power supply terminal to receive power-on voltage according to the comparison power-on sequencing apparatus 100.
An output of the band gap voltage reference 140 is connected through a voltage reference status line 145 to a control logic block 170. An output of the read charge pump 150 is connected through a charge pump status line 155 to the control logic block 170. An output of the circuit block 160 is connected through a circuit block status line 165 to the control logic 170. An output of the control logic block 170 is a control logic status line 175.
At power-on, a ramping-up of the supply voltage level from a VCC power supply exceeds the magnitude of a voltage reference V1 being compared to within the VCC detector 110. The ramping-up supply voltage level triggers production of an enable signal (not shown) on the VCC status line 115 at an output of the VCC detector 110. The enable signal on the VCC status line 115 is provided to the bandgap voltage reference 140, the read charge pump 150, and the circuit block 160. After receipt of the enable signal, the bandgap voltage reference 140, the read charge pump 150, and the circuit block 160 commence operation with a level of VCC being supplied on the VCC terminal that exceeds the voltage reference V1. By appropriate selection of the magnitude of the voltage reference V1, a sufficient level is reached by the ramping-up VCC supply voltage being reached by the ramping-up VCC supply voltage being supplied to the associated circuits so that proper operation is ensured. The bandgap voltage reference 140, the read charge pump 150, and the circuit block 160 are able to successfully carry out their respective processes given enough voltage from the VCC power supply. Each circuit produces an affirmative status signal (not shown) on the bandgap status line 145, the charge pump status line 155, and the circuit block status line 165 respectively.
FIG. 2 is a circuit diagram of a prior art supply voltage detector 200 corresponding to the VCC detector 110 of FIG. 1. An output of a PMOS pull-up transistor 210 is connected through a voltage detection trigger line 215 to a voltage level detector 230. An input of the PMOS pull-up transistor 210 is connected to VCC. A gate input of the PMOS pull-up transistor 210 is connected to ground. An input of the bias resistor 220 is connected to the output of the PMOS pull-up transistor 210 and is connected through the voltage detection trigger line 215 to the voltage level detector 230. An output of the bias resistor 220 is connected to ground. An output of the voltage level detector 230 is connected to a voltage level detection status line 235.
The ramping-up VCC supply voltage level is provided to an input of the PMOS pull-up transistor 210. A full and unqualified level of conduction is possible through the PMOS pull-up transistor 210 with the gate input connected to ground. The ramping-up VCC supply voltage level produces a resultant increasing channel current through the PMOS pull-up transistor 210 which is provided to an input of the bias resistor 220. The increasing current through the bias resistor produces an increasing VCC trigger voltage VCCT (not shown) on the voltage detection trigger line 215. The increasing VCC trigger voltage VCCT is compared with the magnitude of the voltage reference V1 within the voltage level detector 230. As the ramping-up VCC supply voltage level exceeds the magnitude of the voltage reference V1, a detection signal (not shown) is asserted on a voltage level detection status line 235 which corresponds to the VCC status line 115 (FIG. 1). When it is determined by comparison within the supply voltage detector 200 that the ramping-up VCC supply voltage level exceeds the magnitude of the voltage reference V1, an enable signal is produced on the voltage level detection status line 235 as an output signal from the voltage level detector 230. Correspondingly, the enable signal is present on the VCC status line 115 of FIG. 1.
With reference to FIG. 3, a voltage vs. temperature diagram of a prior art operational region 305 corresponding to FIGS. 1 and 2. An abscissa (T) of the diagram is a potential temperature range of the device. The device's operational temperature ranges from −40° Celsius (C.) to 125° C. along the abscissa. A left-hand ordinate of the diagram corresponds to the VCC power supply voltage applied to the device. An operational portion of the VCC power supply voltage for the device spans a range from 2.7 volts (V) to 3.6 V. A right-hand ordinate of the diagram is a range of the VCC trigger voltage VCCT. An operational range of the VCC trigger voltage VCCT is from 2 V to 2.5 V. The area defined by the device's operational temperature range and operational range of the VCC trigger voltage VCCT is the device's operational region 305.
The VCC trigger voltage VCCT is highly dependent upon a device threshold voltage of the PMOS pull-up transistor 210 and the precision and linear tracking of electrical characteristics of the bias resistor 220. Variations in fabrication processes and temperature fluctuations affect these device characteristics. These result in variations in device characteristics produce a VCC trigger voltage variation zone 310.
In order to ensure that proper operation occurs within the circuitry being supplied by the VCC power supply, a designer of a system incorporating power-on sequencing 100 crafts the supply voltage detector 200 such that a maximum value of the VCC trigger voltage variation zone 310 is less than the minimum value of VCC in the operational region 305. Unfortunately, with a possible wide span of fluctuation in the VCC trigger voltage variation zone 310, a minimum value for the VCC trigger voltage VCCT may be too low to supply sufficient voltage and power to properly operate the circuits being supplied by the ramping-up VCC supply.
In the case of a memory cell, the minimum VCC trigger voltage VCCT may be about 2 volts (i.e., the lower boundary of the VCC trigger voltage variation zone 310). This magnitude of voltage is insufficient to source the read charge pump 130 and the bandgap voltage reference 140 with sufficient power to produce proper operation of these circuits even though affirmative status signals may be produced (but incorrectly) on the charge pump status line 155 and the bandgap status line 145 respectively. As a result, these incorrect status signals are provided to the control logic block 170 and are likely to produce an unpredictable condition in the system due to an incorrect production of the status signaling (not shown) on the control logic status line 175 at the conclusion of the power-on sequence.
It would be desirable to have a capability of producing a stable voltage reference during the ramping-on power sequence that could be used as a basis for determining a sufficient level of the ramping-on VCC voltage. Such a capability would ensure that sufficient power is available to sustain proper operation of the circuitry being supplied and thus eliminate any incorrect status signaling from these devices which would produce erroneous conditions for the system.